library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Automa_F is
PORT(
	Start: in std_logic;
	prev_state: in std_logic_vector (2 downto 0);
	next_state: out std_logic_vector (2 downto 0)
);
end Automa_F;

architecture Behavioral of Automa_F is
	signal next_state_int:std_logic_vector (2 downto 0):=(others=>'0');
begin
	next_state<=next_state_int;
	next_state_process: process(prev_state ,Start)
	begin
		case prev_state is
			when "000"=>
				if(Start='1')then
					next_state_int<="001";
					else
					next_state_int<="000";
				end if;
			when "001"=>
				next_state_int<="010";
			when "010"=>
				next_state_int<="011";
			when "011"=>
				next_state_int<="100";
			when "100"=>
				if(Start='0')then
					next_state_int<="000";
					else
					next_state_int<="100";
				end if;
			when others =>
				next_state_int<="000";
		end case;
	end process;
end Behavioral;			
